ISO/IEC 18372:2004 ED1

Information technology - RapidIO TM interconnect specification

Scope

The electronic version of this International Standard can be <a href="https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fstandards.iso.org%2Fittf%2FPubliclyAvailableStandards%2Findex.html&data=05%7C01%7Cig%40iec.ch%7Cf193cf9827cf42052f2a08db134a45e0%7Ca7637f093d864148997bedcd40bee856%7C0%7C0%7C638124982096849475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=RzhHTnTC3nb4f7J4nA10JTkz7%2B%2BFv1I32tb00LGv1UA%3D&reserved=0">downloaded </a>from the ISO/IEC Information Technology Task Force (ITTF) web site.

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-to-board communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.